1. Field of the Invention
The present invention relates to a flash electrically erasable programmable read only memory (EEPROM) cell. More specifically, the present invention relates to a flash EEPROM cell for use in low-voltage, high-speed, high-density applications, such as in complex programmable logic devices (CPLDs).
2. Related Art
FIG. 1 is a cross sectional view of a conventional EEPROM cell 10, which includes p-type substrate 9, field isolation regions 11, floating gate transistor 12 and select gate transistor 13. EEPROM cell 10 is described in U.S. Pat. No. 5,471,422 by Chang et al. Floating gate transistor 12 includes n+ type source region 20, n+ source/drain region 22, tunnel dielectric 14, floating gate 16, interlayer dielectric layer 29, and control gate 28. Select gate transistor 13 includes n+ source/drain region 22, n+ drain region 24, gate dielectric layer 26, select gate 18 and interlayer dielectric layer 29.
In operation, EEPROM cell 10 is programmed, erased and read in accordance with the Table 200 illustrated in FIG. 2.
To program EEPROM cell 10, a programming voltage of 16 to 20 Volts is applied to drain region 24 and select gate 18, while control gate 28 is grounded (and source region 20 is left floating). Under these conditions, electrons tunnel from floating gate 16 through tunnel dielectric 14 to drain region 24, thereby leaving floating gate 16 positively charged.
To erase EEPROM cell 10, a programming voltage of 16 to 20 Volts is applied to control gate 28, while source region 20, select gate 18 and drain region 22 are connected to ground. Under these conditions, electrons tunnel from the channel region of floating gate transistor 12 through tunnel dielectric 14 to floating gate 16, thereby creating a negative charge on floating gate 16.
To read EEPROM cell 10, the V.sub.cc supply voltage of about 5 Volts is applied to select gate 18, a voltage of about 1 Volt is applied to drain region 24, and control gate 28 and source region 20 are connected to ground. A sense amplifier is used to detect the current between source region 20 and drain region 24. A high current indicates a programmed cell and a low current indicates an erased cell.
FIG. 3 is a circuit diagram of EEPROM cell 10 coupled to a plurality of identical EEPROM cells 10A-10G to form an array. The source regions of these EEPROM cells are commonly connected, thereby limiting this array to use in memory applications, and prohibiting the array from being used in a CPLD application. In CPLD applications, each column of cells needs to have separate source and drain bit lines, so that a feedback voltage may be applied to the source bit lines to limit the total read current in the event that a large number of cells are simultaneously turned on in the same column.
The programming voltage of 16 to 20 Volts required to program and erase EEPROM cell 10 is a relatively high voltage. As lower V.sub.cc supply voltages are implemented (e.g., 3.3 Volts or 2.5 Volts) it becomes difficult, if not impossible, to generate such high programming voltages.
In addition, as the V.sub.cc supply voltage is reduced from 5 Volts to 3.3 Volts, the minimum geometry of the fabricated devices is typically reduced from 0.6 &m to 0.35 &m and smaller. The isolation between individual devices is achieved by relatively thick regions of oxide. The thickness of this oxide is limited by the patterning capabilities of the optical photoresist technology to about 4000 .ANG. for a 0.35 &m process. An isolation oxide of 4000 .ANG. provides adequate isolation for voltages of up to approximately 12 Volts. Such an isolation oxide is therefore inadequate to isolate devices when using a programming voltage of 16 to 20 Volts. As a result, a programming voltage of 16 to 20 Volts cannot be used in devices which are fabricated using a 0.35 &m process.
It would therefore be desirable to have a flash EEPROM cell that operates in response to a V.sub.cc supply voltage of 3.3 Volts or lower, and can be programmed and erased with on-chip voltages that are limited to 12 Volts or less.
Another two-transistor memory cell is described in more detail in U.S. patent application Ser. No. 08/722,645 entitled "Two Transistor Flash EPROM Cell" by Anders T. Dejenfelt, Kameswara K. Rao and George H. Simmons, filed Sep. 27, 1996. However, the programming mechanism of this memory cell is hot-electron channeling, which requires relatively a high supply voltage (i.e., 5 Volts) and relatively high programming currents.
U.S. Pat. No. 5,432,740 by D'Arrigo et al. describes an EEPROM memory cell having a merged pass transistor. This memory cell is not well suited for use in a high speed CPLD for two reasons. First, during a read operation, selected word lines are biased at a voltage of +5 Volts, and non-selected word lines are biased at a voltage of -5 Volts. Switching a word line therefore involves a voltage swing of 10 Volts. A relatively long time period is required to complete a switching operation having such a large voltage swing. As a result, the switching time for the word lines of the memory cells of D'Arrigo are undesirably long, thereby rendering the memory cells impractical for use in a high speed CPLD.
In addition, within a CPLD, multiple rows of memory cells can be simultaneously enabled. In contrast, only a single row of memory cells is enabled at any given time within a conventional memory array. It is therefore possible for many more word lines to be simultaneously switched in a CPLD. If the memory cells of D'Arrigo were used in a CPLD, a relatively large number of associated word lines could be switched at any given time. However, it is impractical to build a charge pump having the capacity to supply the current required to simultaneously switch a large number of word lines between -5 Volts and +5 Volts.
Accordingly, it would also be desirable to have a flash EEPROM cell structure that can be coupled in an array to form a high-speed device, such as a CPLD.